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Counter Based Hardware Resource Reduction for FIMA SystemVerilog Assertion Checker

Maoyu Mao

Guangdong University of Science & Technology, Dongguan, Guangdong, 523083, China.

*Corresponding author: Maoyu Mao

Published: November 29,2022 How to cite this paper


Nowadays checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. Several works have been proposed to synthesize assertion checkers on FPGA based emulation and FIMA-based (Finite Input Memory Automaton based) method is one of such works. FIMA-based method uses a finite input-memory automaton using finite input queue (shift-register chain) to transform SVAs to hardware checkers for FPGA prototyping. FIMA-based method keeps one queue for each input, so it is effective to share the queue on several assertions. However, if an assertion includes a long sequence of some input, then the queue becomes long and a lot of hardware resources are necessary. In the research, a method to cope with assertions including such long sequences has been devised, and counter based method is proposed. A binary counter can represent the length N sequence with log(N) bits and the number of registers can be reduced a lot for long sequences. The proposed method can also reduce the power consumption of the sift-registers. Registers in counter module and registers for each variables can be recycled, thus the sharing within time window and sharing between assertions can be achieved. By using embedded RAM modules, we can further save logic element. The counter based method did reduce the hardware resource for FIMA-based method, and it works extremely well for assertions with long sequence of input and less variables.

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How to cite this paper

Maoyu Mao. Counter Based Hardware Resource Reduction for FIMA SystemVerilog Assertion Checker. OA Journal of Computer Networking, 2022, 1(2), 28-39.

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