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Nowadays checker synthesis for assertion based verification becomes popular because of the recent progress on the FPGA prototyping environment. Several works have been proposed to synthesize assertion checkers on FPGA based emulation and FIMA-based (Finite Input Memory Automaton based) method is one of such works. FIMA-based method uses a finite input-memory automaton using finite input queue (shift-register chain) to transform SVAs to hardware checkers for FPGA prototyping. FIMA-based method keeps one queue for each input, so it is effective to share the queue on several assertions. However, if an assertion includes a long sequence of some input, then the queue becomes long and a lot of hardware resources are necessary. In the research, a method to cope with assertions including such long sequences has been devised, and counter based method is proposed. A binary counter can represent the length N sequence with log(N) bits and the number of registers can be reduced a lot for long sequences. The proposed method can also reduce the power consumption of the sift-registers. Registers in counter module and registers for each variables can be recycled, thus the sharing within time window and sharing between assertions can be achieved. By using embedded RAM modules, we can further save logic element. The counter based method did reduce the hardware resource for FIMA-based method, and it works extremely well for assertions with long sequence of input and less variables.
 Chengjie, Z. A. N. G., and Shinji Kimura. "Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping." IEICE transactions on fundamentals of electronics, communications and computer sciences 92.6 (2009): 1454-1463.
 System Verilog 3.1 Language Reference Manual, ver.3.1, http://www.eda.org/sv /System Verilog_3.1_final.pdf.
 Sohofi, H., & Navabi, Z. (2014, March). Assertion-based verification for system-level designs. In Quality Electronic Design (ISQED), 2014 15th International Symposium on (pp. 582-588).IEEE.
 Property Specification Language Reference Manual, ver. 3.1, http://www.eda.org/vfv/docs/PSL-v1.1.pdf.
 M. Boule and Z. Zilic, “Incorporating efficient assertion checkers into hardware emulation,” Proc. 23rd IEEE International Conference on Computer Design, pp.221–228, 2005.
 M. Boule and Z. Zilic, “Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation,” Proc. 12th Asia and South Pacific Design Automation Conference, pp.324–329, 2007.
 Altera Corporation, Quartus II Development Software Handbook, 9.1 ed., Mar. 2009.